TXSCLKMD=SCK_OUTPUT, DIVEN=DISABLED, RXCLKSEL=INTERNAL, TXCLKEN=DISABLED, RXCLKEN=DISABLED, TXCLKSEL=INTERNAL, DUTYMD=MORE, RXSCLKMD=SCK_OUTPUT
Clock Control
| INTDIV | Clock Divider Integer Value. |
| FRACDIV | Clock Divider Fractional Value. |
| DUTYMD | Duty Cycle Adjustment Mode. 0 (MORE): When the division is fractional, the clock high time will be greater than 50% (by half of the source clock period). 1 (LESS): When the division is fractional, the clock low time will be greater than 50% (by half of the source clock period). |
| CLKUPD | Clock Divider Update. 1 (UPDATE): Update the clock divider with new values of INTDIV, FRACDIV, and DIVEN. |
| DIVEN | Clock Divider Enable. 0 (DISABLED): Disable the clock divider. 1 (ENABLED): Enable the clock divider. |
| TXCLKSEL | Transmit Clock Select. 0 (INTERNAL): The I2S transmitter is clocked from the internal clock divider. 1 (EXTERNAL): The I2S transmitter is clocked from the SCK pin. |
| RXCLKSEL | Receive Clock Select. 0 (INTERNAL): The I2S receiver is clocked from the internal clock divider. 1 (EXTERNAL): The I2S receiver is clocked from the SCK pin. |
| RESET | I2S Module Reset. 1 (ACTIVE): Reset the I2S module. |
| RXCLKEN | Receive Clock Enable. 0 (DISABLED): Disable the I2S receiver clock. 1 (ENABLED): Enable the I2S receiver clock. |
| TXCLKEN | Transmit Clock Enable. 0 (DISABLED): Disable the I2S transmitter clock. 1 (ENABLED): Enable the I2S transmitter clock. |
| RXSCLKMD | Receive SCK Mode. 0 (SCK_OUTPUT): The I2S receiver SCK signal is an output. 1 (SCK_INPUT): The I2S receiver SCK signal is an input. |
| TXSCLKMD | Transmit SCK Mode. 0 (SCK_OUTPUT): The I2S transmitter SCK signal is an output. 1 (SCK_INPUT): The I2S transmitter SCK signal is an input. |